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Dan's Mac OS-X EDA Page

PythonBased EDA Tools

MyHDL is a Python package for using Python as a hardwaredescription & verification language. MyHDL 0.4 supports theautomatic conversion of a subset of MyHDL code to synthesizableVerilog code. This feature provides a direct path from Pythonto an FPGA or ASIC implementation. For a general overview andstarting point, go here:

http://jandecaluwe.com/Tools/MyHDL/Overview.html


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